
| Position 1: Project Lead | |
| Domain : | Networking |
| Skill set : | Verilog / VHDL, Ethernet, TCP/IP, SPI4.2/Interlacken , Switches, Aggregator, Routers, Access Network, Security….. |
| Experience : | 5-9 Years |
| Qualification: | Bachelors in Electronics and Electrical Engineering |
| Position 2: Project Lead | |
| Domain : | VLSI |
| Skill set : | Verilog / VHDL, PCIe, USB, ARM, Processor Architecture, SoCs, 802.11, Wireless |
| Experience : | 5-9 Years |
| Qualification: | Bachelors in Electronics and Electrical Engineering |
| Position 3: Verification Engineer | |
| Domain : | VLSI |
| Skill set : | 1. Good knowledge in testing/debugging skills and RTL break down. 2. Strong knowledge in System Verilog, functional coverage, assertions. 3. Hands-on experience on SOC and block level verification methodologies. 4. Strong background in ARM based SOCs and MIPS Processor. 5. Background with peripherals like USB, SDIO, Ethernet, PCIe is preferred. 6. Background in 802.11a/b/g/n MAC/BBP verification is a strong plus. 7. Strong knowledge in languages relevant to the ASIC design (VHDL/Verilog) and verification (C/C++, system verilog, verilog). 8. Strong expertise in writing system level tests in C/C++, verilog or VHDL. 9. Working experience on low power based verification (UPF flow). |
| Job Responsibilities : | 1. Individual contributor role in SOC/block level verification with 3-5 years of experience. 2. Verify complex System on Chip ASIC design with multi-processor subsystem. 3. Develop system level tests using verilog, perl, C/C++ and system verilog programming languages. 4. Working on creating SV based testbench and developing test plan at the block level and top level. 5. Working on refining, scripting simulation environment. |
| Experience : | 4 to 7 years of work experience with good verbal and written communication skills |
| Qualification: | Bachelors in Electronics and Electrical Engineering |
| Position 4: Custom Layout Engineers | |
| Domain : | VLSI |
| Skill set & Job Responsibilities : | 1. Successful candidate will create custom layouts of std-cells, data-paths of memories and help in assembling the individual cells to form the complete functional memory. 2. Work will include creating optimized transistor level layouts that are LVS and DRC clean. 3. The candidate is also expected to identify and fix EM, IR, Noise and other backend electrical issues in the layout. 4. Candidate should have had prior experience in laying out std-cells and embedded SRAM blocks. 5. Knowledge of and experience with back-end circuit validation techniques including DRC, LVS, EM, IR, and noise is also a requirement. |
| Experience : | 3 to 4 years of work experience with good verbal and written communication skills |
| Qualification: | Bachelors in Electronics and Electrical Engineering |
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